About the role
<p data-renderer-start-pos="14" data-local-id="7c4a07c6b9ef">We are deploying machine learning directly onto custom hardware – and we want you to help drive it from the ground up. This is an initiative where you'll have the rare opportunity to architect solutions from scratch, influence technical research direction, and see your work drive real impact in one of the most demanding computing environments in the world.</p> <p data-renderer-start-pos="374" data-local-id="a232a52966f2">We build the hardware, the software, and the infrastructure, so when you hit a bottleneck, you can fix it - there's no vendor to wait on and no abstraction layer you're not allowed to touch. If you've ever wanted to push the boundaries of what's computationally possible, this role is for you. We're looking for researchers and experienced engineers from any background. Trading experience is a bonus, not a prerequisite.</p> <p><strong>Your Core Responsibilities</strong></p> <ul> <li data-renderer-start-pos="827" data-local-id="3d8f27672cb3">Architect and co-design ML models with traders, quant researchers, and software engineers, treating hardware constraints (latency budgets, resource limits, numerical precision) as first-class design inputs</li> <li data-renderer-start-pos="1036" data-local-id="e4081dba3255">Shape our custom hardware roadmap by translating ML model requirements into concrete architectural decisions</li> <li data-renderer-start-pos="1148" data-local-id="2adc2165f97e">Work hands-on with hardware engineers to implement, verify, and deploy ML inference solutions from proof-of-concept through production</li> <li data-renderer-start-pos="1286" data-local-id="a39313dd0463">Track and evaluate emerging research in neural architecture search, machine learning systems and quantization methods, and determine what translates to measurable improvements in our systems</li> </ul> <p><strong>Your Skills and Experience</strong></p> <ul> <li data-renderer-start-pos="1510" data-local-id="f9874e7528e2">Solid understanding of hardware constraints and design trade-offs (e.g., pipelining, resource utilization, fixed-point arithmetic) that shape how ML models can be efficiently mapped onto FPGAs or custom ASICs</li> <li data-renderer-start-pos="1722" data-local-id="d265ff5d3d92">Experience with hardware fundamentals, whether through <span data-highlighted="true" data-vc="highlighted-text"><span class="_kqswh2mm"><span class="_5pioz8co _189e1dm9 _1il9buyh _19lc184f _d0altlke" data-testid="definition-highlighter">VHDL</span></span></span>/SystemVerilog developme