DFT Engineer, Automotive Robotics

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>As part of Tenstorrent’s Automotive Robotics team, you will help design and deliver the core hardware modules inside our next generation chiplet based SoCs for automotive products. You will be the bridge between silicon design, DFT, OSAT partners, and customers to ensure our multi die SiP platforms meet aggressive performance, quality, and safety targets.</p> <p><em>This role is remote, based in Munich, Germany.</em></p> <p><em>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</em></p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>Experienced with industry standard ATPG and DFx insertion CAD tools.</li> <li>Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.</li> <li>Able to translate system and safety requirements into concrete constraints on package architecture, DFT insertion, and support test engineering with planning, patterns, and debug.</li> <li>Comfortable working in a cross functional role that extends beyond DFT, including low power designs with multiple clock domains.</li> <li>Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.</li> <li>Exposure to post-silicon testing and tester pattern debug are major assets.</li> <li>Experience with Fault Campaigns a plus.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Define DFx strategy for multi chiplet packages from architecture through high volume production.</li> <li>10+ years of experience working across multiple teams and multiple companies to coordinate test, yield, and quality efforts.</li> <li>Feed lessons learned back into next generation SiP architectures, DFT strategy, and test content.</li> <li>MBIST, LBIST, IST planning, implementation, and verification.</li> <li>JTAG, Scan Compressi