Machine Learning Engineer (NCG 2026)

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><div data-olk-copy-source="MessageBody">AI/ML Engineer - Silicon Development Automation</div> <div> </div> <div>Position Overview</div> <div>We are seeking an AI/ML Engineer to design and implement AI-enabled workflows that accelerate silicon development processes across the chip design lifecycle. You will apply deep learning and generative AI techniques to optimize EDA (Electronic Design Automation) workflows, spanning frontend design through backend physical design and Design-for-Test (DFT) implementation.</div> <div> </div> <div>Key Responsibilities</div> <div>Workflow Development & Optimization</div> <div>- Develop AI-enabled automation solutions for frontend and backend silicon development domains including circuit design, design verification, formal verification, static code analysis,   debugging, or for backend physical design workflows.</div> <div>- Contribute to agentic workflows that coordinate silicon development tasks</div> <div> </div> <div>AI/ML Model Development</div> <div>- Implement Generative AI systems using Context Engineering, Retrieval-Augmented Generation (RAG) and Agentic techniques  to integrate domain-specific EDA tooling with LLM capabilities</div> <div>- Apply context engineering techniques to encode chip design constraints and specifications into model inputs</div> <div>- Participate in building evaluation suites and internally relevant benchmark data for silicon development AI applications</div