Risc-V Architect

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Our Tensix Team is building the future of AI compute with a ground-up architecture centered on scalable RISC-V processors. As we push performance boundaries, we’re reimagining the frontend of our RISC-V cores to deliver major gains in programmability, efficiency, and developer experience. This is a rare opportunity to shape the CPU architecture at the heart of our AI platform and lead one of the most strategic technical efforts at Tenstorrent.</p> <p>This role is hybrid, based out of Toronto, ON or Austin, TX.</p> <p>We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>An experienced architect with over 10 years in CPU performance modeling and microarchitecture.</li> <li>Proficient in C++ and Python, with a strong understanding of RISC-V instruction-set.</li> <li>Well versed in compiler design and how software stacks impact CPU performance and programmability.</li> <li>Familiar with open-source RISC-V cores and LLVM toolchains, including adding custom optimization passes.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Analyze AI workloads to identify CPU performance requirements and bottlenecks.</li> <li>Architect custom RISC-V CPU cores optimized for performance, power, and area.</li> <li>Design custom instructions that improve performance without sacrificing programmability.</li> <li>Collaborate across compilers, software, and hardware teams to co-design Tenstorrent’s next-gen compute architecture.</li> </ul> <p> </p> <p><strong>What You Will Learn</strong></p> <ul> <li>How modern AI models stress CPU architecture and influence design decisions.</li> <li>The interplay between compiler design, CPU microarchitecture, and real-world performance.</li> <li>How Tenstorrent’s unified hardware-s